ScanMaster PXI is a powerful, high speed JTAG (IEEE 1149.1) controller designed for use in a standard PXI chassis for design verification, production test, and on-board device programming applications. Utilising its proprietary JPXI™ bus-master with high speed cache memory behind TDI and TDO, Adaptive Clocking™ technology, and a 32-bit bus architecture, ScanMaster PXI eliminates bottlenecks to data delivery. This is critical to applications like Flash programming where large amounts of data must be processed and delivered. From the exchange of data with the host computer through to delivery of vectors to targets, ScanMaster PXI™ has been designed for high bandwidth, which enables delivery of data at speeds up to 25 Mbits/Sec.

Adaptive Clocking eliminates instabilities typically associated with boundary scan (JTAG) operation at high clock rates (TCK) due to path delays. This proprietary and patented design compensates for path delays allowing the JPCI controller to operate at the maximum TCK rate supported by the target devices, and with up to 15 meters of cable between the JPCI controller and target devices. Without Adaptive Clocking, users are forced to either reduce cable length, leading to impractical set-ups which pose extreme limitation on application of Boundary Scan in a real production environment, or reduce TCK rate, which will in turn reduce throughput.

If you require further information regarding this or any other product, please detail your query in the form below.

Tel: +44 (0) 1462 742499
Fax: +44 (0) 1462 742497
Email: info@terotest.com

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